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feds81v05200-01 1 semiconductor this version: jun. 2001 MS81V05200 (583,680-word 10-bit) fifo memory 1/25 general description the MS81V05200 is a 5.6mb fifo (first-in first-out) memory designed for 583,680-words 10-bit high-speed asynchronous read/write operation. the MS81V05200 is best suited for a field memory for digital tvs or lcd panels which require high-speed, large memory, and is not designed for high end use in professional graphics systems, which require long term picture storage and data storage. the MS81V05200 is provided with independent control clocks to support asynchronous read and write operations. different clock rates are also supported, which allow alternate data rates between write and read data streams. the first data read operation can be performed after 1600 ns + 4 cycles from read reset and the first data write operation is enabled after 1600 ns + 4 cycles from write reset. thereafter, the high-speed read/write operation is possible every cycle time. additionally, a write mask function by ie pin and a read-data skipping function by oe pin implement image data processing easily. the MS81V05200 provides high speed fifo (first-in first-out) operation without external refreshing: MS81V05200 refreshes its dram storage cells automatically, so that it appears fully static to the users. moreover, fully static type memory cells and decoders for serial access enable the refresh free serial access operation, so that serial read and/or write control clock can be halted high or low for any duration as long as the power is on. internal conflicts of memory access and refreshing operations are prevented by special arbitration logic. the MS81V05200?s function is simple, and similar to a digital delay device whose delay-bit- length is easily set by reset timing. the delay length and the number of read delay clocks between write and read, is determined by externally controlled write and read reset timings. the MS81V05200 uses a thin and small 70-pin plastic tsop. features ? 583,680 words 10 bits ? fast fifo (first-in first-out) operation: 13 ns cycle time ? self refresh (no refresh control is required) ? high speed asynchronous read/write operation ? variable length delay bit (600 to 583,680) ? single power supply: 3.3 v 0.3 v ? package: 70-pin plastic tsop type ii (tsop(2) 70-p-400-0.5-k) parameters parameter symbol MS81V05200-ta access time t ac 8 ns read/write cycle time t swc t src 13 ns operation current i cc1 200 ma standby current i cc2 6 ma
feds81v05200-01 1 semiconductor MS81V05200 2/25 pin configuration (top view) v cc cs csmode nc v ss di0 di1 nc di2 v ss do0 do1 v cc nc do2 v ss v ss v cc v cc do3 nc v cc nc do4 v ss di3 nc nc di4 v ss oe re rstr srck v cc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 v ss nc nc nc v cc di9 di8 nc di7 v ss do9 do8 v cc nc do7 v ss v ss v cc v cc do6 nc v cc nc do5 v ss di6 nc nc di5 v cc ie we rstw swck v ss 70-pin plastic tsop swck serial write clock srck serial read clock we write enable re read enable ie input enable oe output enable rstw reset write rstr reset read di0-9 data input do0-9 data output cs chip select csmode chip select mode v ss ground (0 v) v cc power supply (3.3 v) nc no connection note: the same power supply voltage must be provided to every v cc pin, and the same gnd voltage level must be provided to every v ss pin.
feds81v05200-01 1 semiconductor MS81V05200 3/25 block diagram refresh counter data-output buffer read data register x decoder (x10) serial read controller (x16) serial write controller data-input buffer read/write refresh timing generator do (x10) oe re rstr srck di (x10) ie we rstw swck 583,680 10 memory array write data register
feds81v05200-01 1 semiconductor MS81V05200 4/25 pin description data inputs: (di0-9) these pins are used for serial data inputs. write reset: rstw the first positive transition of swck after rstw becomes high resets the write address pointers to zero. rstw setup and hold times are referenced to the rising edge of swck. write enable: we we is used for data write enable/disable control. we high level enables the input, and we low level disables the input and holds the internal write address pointer. there are no we disable time (low) and we enable time (high) restrictions, because the MS81V05200 is in fully static operation as long as the power is on. note that we setup and hold times are referenced to the rising edge of swck. the latency for the write operation control by we is 4. after write reset, we must remain low for more than 1600 ns (t fwd ). after write reset, the write operation at address 0 is started after a time t wl form the cycle in which we is brought high. input enable: ie ie is used to enable/disable writing into memory. ie high level enables writing. the internal write address pointer is always incremented by cycling swck regardless of the ie level. note that ie setup and hold times are referenced to the rising edge of swck. the latency for the write operation control by ie is 4. data out: (do0-9) these pins are used for serial data outputs. read reset: rstr the first positive transition of srck after rstr becomes high resets the read address pointers to zero. rstr setup and hold times are referenced to the rising edge of srck. read enable: re the function of re is to gate of the srck clock for incrementing the read pointer. when re is high before the rising edge of srck, the read pointer is incremented. when re is low, the read pointer is not incremented. re setup times (t rens and t rdss ) and re hold times (t renh and t rdsh ) are referenced to the rising edge of the srck clock. the latency for the read operation control by re is 4. after read reset, re must remain low for more than 1600 ns (t frd ). after read reset, the read data at address 0 is output after a time t rl from the cycle in which we is brought high. output enable: oe oe is used to enable/disable the outputs. oe high level enables the outputs. the internal read address pointer is always incremented by cycling srck regardless of the oe level. note that oe setup and hold times are referenced to the rising edge of srck. the latency for the read operation control by oe is 4. serial write clock: swck the swck latches the input data on chip when we is high, and also increments the internal write address pointer. data-in setup time t ds , and hold time t dh are referenced to the rising edge of swck. serial read clock: srck data is shifted out of the data registers. it is triggered by the rising edge of srck when re is high during a read operation. the srck input increments the internal read address pointer when re is high. the three-state output buffer provides direct ttl compatibility (no pullup resistor required). data out is the same polarity as data in. the output becomes valid after the access time interval tac that begins with the rising edge of srck. *there are no output valid time restriction on MS81V05200.
feds81v05200-01 1 semiconductor MS81V05200 5/25 absolute maximum ratings parameter symbol condition rating unit power supply voltage v cc ta = 25c ?0.5 to +4.6 v input output voltage v t ta = 25c, v ss ?0.5 to +4.6 v output current i os ta = 25c 50 ma power dissipation p d ta = 25c 1 w operating temperature t opr ? 0 to 70 c storage temperature t stg ? ?55 to +150 c recommended operating conditions parameter symbol min. typ. max. unit power supply voltage v cc 3.0 3.3 3.6 v input high voltage v ih 2.0 v cc v cc + 0.2 v input low voltage v il ?0.3 0 0.8 v electrical characteristics dc characteristics parameter symbol condition min. max. unit input leakage current i li 0 < v i < v cc , other pins tested at v = 0 v ?10 +10 a output leakage current i lo 0 < v o < v cc ?10 +10 a output ?h? level voltage v oh i oh = ?2 ma 2.4 ? v output ?l? level voltage v ol i ol = 2 ma ? 0.4 v operating current i cc1 minimum cycle time output open ? 200 ma standby current i cc2 input pin = v ih /v il ?6 ma capacitance (v cc = 3.3 v 0.3 v, ta = 25c, f = 1 mhz) parameter symbol max. unit input capacitance c i 5pf output capacitance c o 7pf
feds81v05200-01 1 semiconductor MS81V05200 6/25 ac characteristics (v cc = 3.3 v 0.3 v, ta = 0 to 70c) parameter symbol min. max. unit dout access time from srck t ac ?8ns dout hold time from srck t ddck 3?ns dout enable time from srck t deck 38ns swck ?h? pulse width t wswh 4?ns swck ?l? pulse width t wswl 4?ns input data setup time t ds 3?ns input data hold time t dh 1?ns we enable setup time t wens 3?ns we enable hold time t wenh 1?ns we disable setup time t wdss 3?ns we disable hold time t wdsh 1?ns ie enable setup time t iens 3?ns ie enable hold time t ienh 1?ns ie disable setup time t idss 3?ns ie disable hold time t idsh 1?ns we ?h? pulse width t wweh 4?ns we ?l? pulse width t wwel 4?ns ie ?h? pulse width t wieh 4?ns ie ?l? pulse width t wiel 4?ns rstw setup time t rstws 3?ns rstw hold time t rstwh 1?ns srck ?h? pulse width t wsrh 4?ns srck ?l? pulse width t wsrl 4?ns re enable setup time t rens 3?ns re enable hold time t renh 1?ns re disable setup time t rdss 3?ns re disable hold time t rdsh 1?ns oe enable setup time t oens 3?ns oe enable hold time t oenh 1?ns oe disable setup time t odss 3?ns oe disable hold time t odsh 1?ns re ?h? pulse width t wreh 4?ns re ?l? pulse width t wrel 4?ns oe ?h? pulse width t woeh 4?ns oe ?l? pulse width t woel 4?ns rstr setup time t rstrs 3?ns rstr hold time t rstrh 1?ns swck cycle time t swc 13 ? ns srck cycle time t src 13 ? ns transition time (rise and fall) t t 15ns we ?l? period before w reset t lwe 4?clk re ?l? period before r reset t lre 4?clk re delay after reset t frd 1,600 ? ns we delay after reset t fwd 1,600 ? ns
feds81v05200-01 1 semiconductor MS81V05200 7/25 parameter symbol latency unit write latency t wl 4clk read latency t rl 4clk we write control latency t wel 4clk ie write control latency t iel 4clk re read control latency t rel 4clk oe read control latency t oel 4clk ac characteristic measuring conditions output compare level 1.4 v output load 1 ttl + 30 pf input signal level 3.0 v/0.0 v input signal rise/fall time 1 ns input signal measuring reference level 1.4 v note: input voltage levels for the ac characteristic measurement are v ih = 3.0 v and v il = 0 v. when transition time t t becomes 1 ns or more, the input signal reference levels for the parameter measurement are v ih (min.) and v il (max.).
feds81v05200-01 1 semiconductor MS81V05200 8/25 operation mode write operation cycle the write operation is controlled by four control signals, swck, rstw, we, and ie. the write operation is accomplished by cycling swck, and holding we high after the write address pointer reset operation or rstw. rstw must be performed for internal circuit initialization before write operation. we must be low before and after the reset cycle (t lwe + t fwd ). each write operation, which begins after rstw must contain at least 231 active write cycles, i.e., swck cycles while we and ie are high. settings of we and ie to the operation mode of write address pointer and data input we ie internal write address pointer data input (latency 4) h h input hl incremented lx halted not input x indicates ?don?t care? read operation cycle the read operation is controlled by four control signals, srck, rstr, re, and oe. the read operation is accomplished by cycling srck, and holding both re and oe high after the read address pointer reset operation or rstr. each read operation, which begins after rstr, must contain at least 231 active read cycles, i.e., srck cycles while re and oe are high. re must be low before and after the reset cycle (t lre + t fwd ). settings of re and oe to the operation mode of read address pointer and data output re oe internal read address pointer data output (latency 4) h h output hl incremented high impedance l h output ll halted high impedance old/new data access there must be a minimum delay of 600 swck cycles between writing into memory and reading out from memory. if reading from the first field starts with an rstr operation, before the start of writing the second field (before the next rstw operation), then the data just written will be read out. the start of reading out the first field of data may be delayed past the beginning of writing in the second field of data for as many as 70 swck cycles. if the rstr operation for the first field read-out occurs less than 70 swck cycles after the rstw operation for the second field write-in, then the internal buffering of the device assures that the first field will still be read out. the first field of data that is read out while the second field of data is written is called ?old data?. in order to read out ?new data?, i.e., the second field written in, read reset must be input after write address 200 the delay between an rstw operation and an rstr operation must be at least 600 srck cycles. if the delay between rstw and rstr operations is more than 71 but less than 600 cycles, then the data read out will be undetermined. it may be ?old data? or ?new data?, or a combination of old and new data. such a timing should be avoided. when the read address delay is between more than 71 and less than 599 or more than 583,680, read data will be undetermined. however, normal write is achieved in this address condition.
feds81v05200-01 1 semiconductor MS81V05200 9/25 timing diagram write cycle timing (write reset) write cycle timing (write enable) t swc 0 c y cle t wswh swck rstw di0-9 we ie t rstws t rstwh t fwd t lwe t dh t ds t wl dn-3 dn-2 dn-1 dn t wswl d0 d1 di0-9 rstw t wel t wens d5 d4 d3 d2 d1 d0 d7 d6 1 cycle 2 cycle 3 c y cle 4 cycle 5 cycle 6 cycle t wdss t wdsh t wenh swck we ie l h t wweh t wwel
feds81v05200-01 1 semiconductor MS81V05200 10/25 write cycle timing (input enable) t iel t iens d5 d4 d3 d2 d1 d0 d11 d10 1 c y cle 2 c y cle 3 c y cle 4 c y cle 5 c y cle t idss t idsh t ienh swck ie di0-9 rstw we l h 6 cycle 7 cycle 8 cycle 9 cycle 10 cycle t wieh t wiel
feds81v05200-01 1 semiconductor MS81V05200 11/25 read cycle timing (read reset) read cycle timing (read enable) t rel t rens 1 cycle 2 c y cle 3 cycle 4 c y cle 5 cycle 6 cycle t rdss t rdsh t renh srck re do0-9 rstr oe l h q0 q5 q1 q2 q6 q7 q3 q4 t ac t wreh t wrel t src 0 cycle t wsrh 1 cycle srck rstr do0-9 re oe t rstrs t rstrh t frd t lre t rl qn-3 qn t wsrl qn-2 qn-1 q0 q1 t ac h
feds81v05200-01 1 semiconductor MS81V05200 12/25 read cycle timing (output enable) do0-9 t oel t oens 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle t odss t odsh t oenh srck oe rstr re l h q0 q5 q1 q2 q10 q11 q3 q4 t ac t woeh t woel t ddck t deck 6 cycle 7 cycle 8 cycle 9 cycle 10 cycle 11 cycle
feds81v05200-01 1 semiconductor MS81V05200 13/25 write cycle timing di0-9 ie we rstw swc k t fwd t wl 01 0 1 234 56 78 1011 12 a0 a1 a2 xi a98 a99 a100 t wel b0 b1 b2 b3 b4 b5 b6 b7 b8 b9 b11 98 99 2 t iel 9
feds81v05200-01 1 semiconductor MS81V05200 14/25 read cycle timing re src k oe do0-9 rstr t frd t rl 012 0 1 2 3456 78910 11 12 a0 a1 a2 xi a95 a96 a97 b0 b1 b2 b3 b4 b5 b6 b7 b8 b9 t rel t oel b11 t ac 96 97
feds81v05200-01 1 semiconductor MS81V05200 15/25 read/write cycle timing (new data read) di0-9 ie re src k oe do0-9 rstr we rstw swc k t frd t rl 0 xi a0 a1 t ac read reset should be input after write address 200. t fwd t wl 199 200 201202 a0 a1 a2 xi 96 97 98 292 293 294 295 296 xi?2 xi?3 012 i 1 2 96 97 i xi?1 the address difference is 600 or more and 583,679 or less.
feds81v05200-01 1 semiconductor MS81V05200 16/25 read/write cycle timing (old data read) di0-9 ie re src k oe do0-9 rst r t fwd t wl the address difference is 70 or less. t frd t rl 012 xi a0 a1 a2 a3 a4 a0 a1 a2 xi 012 34 we rstw swc k i i
feds81v05200-01 1 semiconductor MS81V05200 17/25 pin description chip select mode (csmode) this pin determines the polarity of the chip select (cs) pin. always connect the csmode pin to v cc or v ss or leave it open. chip select (cs) this pin enables or disables devices (rstw, we, ie, rstr, re, and oe). the polarity of the cs pin is dependent upon the level of the csmode pin. in case where the csmode pin is connected to v ss or left open: when chip select (cs) is high, the device is enabled and ready for read/write operation. when chip select (cs) is low, the device is disabled and the internal write/read address pointer stops. writing in the device is suppressed. the output of the pin goes to high impedance. in case where the csmode pin is connected to v cc : when chip select (cs) is low, the device is enabled and ready for read/write operation. when chip select (cs) is high, the device is disabled and the internal write/read address pointer stops. writing in the device is suppressed. the output of the pin goes to high impedance. csmode cs device state h enabled v ss or open l disabled h disabled v cc l enabled the write/read operation is reset as follows: in case where the csmode pin is connected to v ss or left open: on the rising edge of swck, a write operation is reset when both rstw and cs are high. on the rising edge of srck, a read operation is reset when both rstr and cs are high. in case where the csmode pin is connected to v cc : on the rising edge of swck, a write operation is reset when rstw is high and cs is low. on the rising edge of srck, a read operation is reset when rstr is high and cs is low. in this case, the cs setup time (t rwcss /t rrcss ) and the cs hold time (t rwcsh /t rrcsh ) must be satisfied relative to the rising edge of swck/srck in the reset cycle. when cs and csmode set the ?disabled? device state, the rstw/rstr input is invalid. satisfy the following conditions before causing cs to make a transition: ? pull we, ie, re, and oe low respectively for times t wecss , t iecss , t recss , and t oecss before causing cs to make a transition. ? enter five or more swck and srck cycles during times t wecss , t iecss , t recss , and t oecss , and then cause cs to make a transition. (a write operation requires five cycles or more of t wlcsa and t wlcsb . a read operation requires five cycles or more of t rlcsa and t rlcsb .) ? cause cs to make a transition only when rstw and rstr are low. ? pull we, ie, re, and oe low respectively for times t wecsh , t iecsh , t recsh , and t oecsh after causing cs to make a transition.
feds81v05200-01 1 semiconductor MS81V05200 18/25 operation modes (see timing diagram) cs control timing 1 when cs makes a high-to-low transition after data of up to a4/c4 is written in or read from fifo1, fifo1 is disabled and fifo2 is enabled. when cs makes a low-to-high transition after data of up to b7/d7 is written in or read from fifo2, fifo2 is disabled and fifo1 is enabled again. data is written or read starting at a5/c5 in fifo1. (in the ?disabled? device state, the address pointer in the fifo1 remains unchanged.) cs control timing 2 (at reset ) when rstw or rstr is input, write-reset or read-reset is applied only to fifo2 since cs is low. (fifo1 is not reset.) therefore, when fifo1 is enabled again, data is written or read starting at ai+5/ci+5 in fifo1. cs control timing 3 (at reset) when rstw or rstr is input, write-reset or read-reset is applied only to fifo1 (fifo2 is not reset.) therefore, data is written or read starting at bi/di in fifo2. when fifo1 is enabled again, data is written or read again starting at a0/c0 in fifo1 since the internal address pointer is already reset. power-up and initialization on power-up, the device is designed to begin proper operation after at least 200 s after vcc has stabilized to a value within the range of recommended operating conditions. after this 200 s stabilization interval, the following initialization sequence must be performed. because the read and write address pointers are undefined after power-up, a minimum of 330 dummy write operations (swck cycles) and read operations (srck cycles) must be performed, followed by an rstw operation and an rstr operation, to properly initialize the write and the read address pointer.
feds81v05200-01 1 semiconductor MS81V05200 19/25 ac characteristics (cs control) parameter symbol min. max. units cs-we setup time t wecss 68 ? ns cs-we hold time t wecsh 23 ? ns cs-ie setup time t iecss 68 ? ns cs-ie hold time t iecsh 23 ? ns cs-re setup time t recss 68 ? ns cs-re hold time t recsh 23 ? ns cs-oe setup time t oecss 68 ? ns cs-oe hold time t oecsh 23 ? ns cs ?h? pulse width t csh 4200 ? ns cs ?l? pulse width t csl 4200 ? ns swck-cs setup time at rstw cycle t rwcss 8?ns swck-cs hold time at rstw cycle t rwcsh 8?ns srck-cs setup time at rstr cycle t rrcss 8?ns srck-cs hold time at rstr cycle t rrcsh 8?ns dummy swck cycle before cs state transition t wlcsa 4?clk final dummy swck period of cs t wlcsb 13 ? ns dummy srck cycle before cs state transition t rlcsa 4?clk final dummy srck period of cs t rlcsb 13 ? ns
feds81v05200-01 1 semiconductor MS81V05200 20/25 cs control circuit example 1) fifo1 swck rstw we ie di0-9 cs csmode srck rstr re oe do0-9 MS81V05200 fifo2 swck rstw we ie di0-9 cs csmode srck rstr re oe do0-9 MS81V05200 v ss or open v cc swck rstw we ie di0-9 cs srck rstr re oe do0-9
feds81v05200-01 1 semiconductor MS81V05200 21/25 cs control timing 1 swck (fifo1/2) rstw (fifo1/2) di0-9 (fifo1) we (fifo1/2) srck (fifo1/2) rstr (fifo1/2) re (fifo1/2) cs (fifo1/2) do0-9 (fifo1) do0-9 (fifo2) di0-9 (fifo2) ie (fifo1/2) oe (fifo1/2) t wecss t wecsh t iecss t iecsh t recss t recsh t oecss t oecsh c0 c 1 c 2 c3 c 4 d0 d1 d2 d3 d4 d5 d6 d7 c5 c6 c7 c8 a0 a1 a2 a3 a4 b0 b1 b2 b3 b4 b5 b6 b7 a5 a6 a7 a8 t ac t wecss t wecsh t iecss t iecsh t recss t recsh t oecss t oecsh t csl t rlcsa t rlcsa t wlcsa t wlcsa t wlcsb t rlcsb t wlcsb t rlcsb csmode (fifo1) csmode (fifo2) v cc v ss or open fifo1 enable1 fifo2 enable1 fifo1 enable2 (continued from enable1)
feds81v05200-01 1 semiconductor MS81V05200 22/25 cs control timing 2 (reset timing) swck (fifo1/2) rstw (fifo1/2) di0-9 (fifo1) w e (fifo1/2) srck (fifo1/2) rstr (fifo1/2) re (fifo1/2) cs (fifo1/2) do0-9 (fifo1) do0-9 (fifo2) di0-9 (fifo2) ie (fifo1/2) oe (fifo1/2) t wecss t fwd t iecss t iecsh t recss t frd t oecss t oecsh ci ci+1 ci+2 ci+3 ci+4 d0 d1 d2 d3 d4 d5 d6 d7 ci+5 ci+6 ci+7 ci+8 b0 b1 b2 b3 b4 b5 t ac t wecss t wecsh t iecss t i ecsh t recss t recsh t oecss t oecsh t csl t rlcsa t rlcsa t wlcsa t wlcsa t rwcss t rrcss di t rlcsb t wlcsb t wlcsb t rlcsb csmode (fifo1) csmode (fifo2) v cc v ss or open fifo1 enable1 fifo2 enable1 (reset operation) fifo1 enable2 (continued from enable1) ai+5 ai+6 ai+7 ai+8 ai ai+1 ai+2 ai+3 ai+4
feds81v05200-01 1 semiconductor MS81V05200 23/25 cs control timing 3 (reset timing) csmode (fifo1) csmode (fifo2) v cc v ss or open swck (fifo1/2) rstw (fifo1/2) di0-9 (fifo1) w e (fifo1/2) srck (fifo1/2) rstr (fifo1/2) re (fifo1/2) cs (fifo1/2) do0-9 (fifo1) do0-9 (fifo2) di0-9 (fifo2) ie (fifo1/2) oe (fifo1/2) t wecss t iecss t recss t oecss ci ci+1 ci+2 ci+3 ci+4 ci+5 di+1 di+2 di+3 di+4 di+5 di+6 c0 c1 c2 c3 a0 a1 a2 a3 t ac t wecss t wecsh t iecss t iecsh t recss t recsh t oecss t oecsh t csl t rlcsa t rlcsa t wlcsa t wlcsa t rwcsh t rrcsh di t wlcsb t rlcsb t wlcsb t rlcsb t wecsh t iecsh t recsh t oecsh fifo1 enable1 (reset operation) fifo2 enable1 fifo1 enable2 (continued from enable1) ai ai+1 ai+2 ai+3 ai+4 ai+5 bi+1 bi+2bi+3 bi+4 bi+5 bi
feds81v05200-01 1 semiconductor MS81V05200 24/25 package dimensions (unit: mm) tsop(2)70-p-400-0.50-k mirror finish package material epoxy resin lead frame material 42 alloy pin t r e a t m ent so l der p l at i ng ( 5 m) packa g e w e i g ht ( g ) 0 .49 t y p . 5 rev. no./last revised 2/nov. 13, 1998 notes for mounting the surface mount type package the surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. therefore, before you perform reflow mounting, contact oki?s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
feds81v05200-01 1 semiconductor MS81V05200 25/25 notice 1. the information contained herein can change without notice owing to product and/or technical improvements. before using the product, please make sure that the information being referred to is up-to-date. 2. the outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. when planning to use the product, please ensure that the external conditions are reflected in the actual circuit, assembly, and program designs. 3. when designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. 4. oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. 5. neither indemnity against nor license of a third party?s industrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. no responsibility is assumed by us for any infringement of a third party?s right which may result from the use thereof. 6. the products listed in this document are intended for use in general electronics equipment for commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). these products are not authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, and life-support systems. 7. certain products in this document may need government approval before they can be exported to particular countries. the purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these. 8. no part of the contents contained herein may be reprinted or reproduced without our prior permission. copyright 2001 oki electric industry co., ltd.

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